교수소개
교수소개
 학과소개 교수소개 전자공학프로그램
이름
남재원
전공
아날로그 집적회로 설계
TEL
02-970-6478
E-mail
jaewon.nam@seoultech.ac.kr
연구실
창학관 227호
프로필
다운로드
교수소개 돌아가기
학력
University of Southern California, Ph.D.(Electrical Engineering)
주요 경력
◾ ETRI, Daejeon, South Korea
- Graduate Intern (2006.Oct. - 2007.Oct)
- Research Staff (2008.Feb. - 2012.June)

◾ Intel Corporation (DCG), Santa Clara CA, US
- Graduate Intern (2017. Oct - 2017. Dec)

◾ Intel Corporation LTD AD, Hillsboro OR, US
- Analog Engineer (2019. Sept - 2020. July)
연구 분야
◾ Mixed-signal Analog Integrated Circuit Design
◾ Data-converter based Wireline Tx & Rx
◾ Sensor Interface ROIC
◾ Machine-Learning assisted design automation
담당 교과목
◾ 전자회로 (1)
◾ 전자회로 (2)
◾ 창의공학설계
주요논문 및 저서
◾ J.-W. Nam, and M.-W. Chen, “A 12.8-Gbaud ADC-based Wireline Receiver with Embedded IIR Equalizer,” IEEE J. Solid-State Circuits, CICC special edition, Dec. 2019.
◾ J.-W. Nam, M. Hassanpourghadi, A. Zhang, and S.-W. M. Chen, “A 12-bit 1.6, 3.2, and 6.4 GS/s 4-b/cycle Time-Interleaved SAR ADC with Dual Reference Shifting and Interpolation,” IEEE J. Solid-State Circuits, vol. 53, no. 6, pp. 1765-1779, Jun. 2018
◾ J.-W. Nam, and S.-W. M. Chen, “An embedded passive gain technique for asynchronous SAR ADC achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 63, no. 10, pp. 1628 - 1638, Oct. 2016.
저널 논문
◾ J.-W. Nam, and M.-W. Chen, “A 12.8-Gbaud ADC-based Wireline Receiver with Embedded IIR Equalizer,” IEEE J. Solid-State Circuits, CICC special edition, Dec. 2019.
◾ J.-W. Nam, M. Hassanpourghadi, A. Zhang, and S.-W. M. Chen, “A 12-bit 1.6, 3.2, and 6.4 GS/s 4-b/cycle Time-Interleaved SAR ADC with Dual Reference Shifting and Interpolation,” IEEE J. Solid-State Circuits, vol. 53, no. 6, pp. 1765-1779, Jun. 2018
◾ J.-W. Nam, and S.-W. M. Chen, “An embedded passive gain technique for asynchronous SAR ADC achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 63, no. 10, pp. 1628 - 1638, Oct. 2016.
◾ J.-W. Nam, Y.-D. Jeon, Y.-K. Cho, J.-K. Kwon, “A 12-Bit 200-MS/s pipelined A/D converter with sampling skew reduction technique,” Elsevier Microelectronics Journal, no. 11, vol. 42, pp. 1225-1230, Nov. 2011.
◾ Y.-D. Jeon, J.-W. Nam, K.-D. Kim, T. M. Roh, and J.-K. Kwon, “A dual-channel pipelined ADC with sub-ADC based on flash–SAR architecture,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 11, pp. 741–745, Nov. 2012.
◾ H. B. Le, J.-W. Nam, S.-T. Ryu, and S.-G. Lee, “Single-chip A/D converter for digital microphones with on-chip preamplifier and time-domain noise isolation,” Electronics Letter, vol. 45, no. 3, pp. 151-153, 2009.
◾ Y.-K. Cho, Y.-D. Jeon, J.-W. Nam, and J.-K. Kwon, “A 9-bit 80 MS/s successive approximation register analog-to-digital Converter with a capacitor reduction technique,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 7, pp. 502–506, Jul. 2012.
◾ Y.-K. Cho, Y.-D. Jeon, J.-W. Nam, and J.-K. Kwon, “A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications,” Elsevier Microelectronics Journal, vol. 42, no. 12, pp. 1335–1342, Jul. 2011.
◾ Y.-D. Jeon, Y.-K. Cho, J.-W. Nam, S. -C, Lee, and J.-K. Kwon, “A 1.2 V 12 b 60 MS/s CMOS analog front-end for image signal processing applications,” Elsevier ETRI Journal, vol. 31, no. 6, Dec. 2009.
◾ 듀얼 레퍼런스 전압 이동 및 보간법을 활용한 12-bit 1.6, 3.2, and 6.4 GS/s 4-b/cycle 시분할 SAR ADC, 전기전자기술자협회 반도체회로분과, vol.53 No.6 pp.1765~1779, 2018
[원문보기] 남재원
◾ 수동이득단 내재기법을 적용한 비동기식 SAR ADC (10.2 ENOB 1.36-mW at 95-MS/s 65nm CMOS), IEEE 트랜젝션 회로 및 시스템 - I, vol.63 No.10 pp.1628~1638, 2016
[원문보기] 남재원
◾ 플래쉬-SAR 구조를 적용한 듀얼채널 파이프로인 아날로그-디지털 신호변환기, 전기전자기술자협회 회로 및 시스템 분과, vol.59 No.11 pp.741~745, 2012
[원문보기] 남재원
◾ 저전력 서브샘플링 응용분야를 위한 10-bit 30-MS/s 연속근사레지스터 아날로그-디지털 신호변환기, Elsevier 전자회로 저널, vol.42 No.12 pp.1335~1342, 2011
[원문보기] 남재원
◾ 표본화 스큐저감기술을 적용한 12-bit 200-MS/s 파이프라인 아날로그-디지털 신호변환기, Elsevier 전자회로 저널, vol.42 No.11 pp.1225~1230, 2011
[원문보기] 남재원
◾ 커패시터 저감방법을 활용한 9-bit 80 MS/s 연속근사레이지스터 아날로그-디지털 신호변환기, IEEE 회로 및 시스템 II, vol.57 No.7 pp.502~506, 2010
[원문보기] 남재원
◾ A 1.2 V 12 b 60 MS/s CMOS Analog Front-End for Image Signal Processing Applications, ETRI 저널, vol.31 No.6 pp.717~724, 2009
[원문보기] 남재원
학술대회
◾ J.-W. Nam, and M.-W. Chen, “A 12.8-Gbaud ADC-based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter Achieving 2.43-pJ/b in 65nm CMOS,” IEEE Custom Integrated Circuits Conf., Apr, 2019, (Best Student Paper Award).
◾ J.-W. Nam, M. Hassanpourghadi, A. Zhang, and S.-W. M. Chen, “Low-power High Dynamic-range ADC with over GHz Bandwidth using Cost-efficient Multi-bit/cycle SAR ADC,” GOMATech 2018.
◾ J.-W. Nam, M. Hassanpourghadi, A. Zhang, and S.-W. M. Chen, “A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2016, pp.154–156.
◾ J.-W. Nam, D. Chiong, and S.-W. M. Chen, “A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65 nm CMOS,” IEEE Custom Integrated Circuits Conf., Sep. 2013, pp. 1–4.
◾ J.-W. Nam, Y.-D. Jeon, S.-J. Yun, T. M. Roh, and J.-K. Kwon, “A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS,” in Proc. IEEE ISOCC, 2011, pp. 405–407.
◾ J.-W. Nam, Y.-D. Jeon, Y.-K. Cho, S.-G. Lee, and J.-K. Kwon, “A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS,” in Proc. IEEE ESSCIRC, 2009, pp. 468–471.
◾ D. Kang, H. Lim, J.-W. Nam, M. S.-W. Chen, J. Yoon, “VCSEL-Based Stretchable Blood Flow Sensors”, A meeting of the materials Research Society, Boston, U.S., Nov. 2017.
◾ Y.-D. Jeon, Y.-K. Cho, J.-W. Nam, W.-Y. Lee, K.-T. Hong, and J.-K. Kwon, “A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS,” IEEE Custom Integrated Circuits Conf., Sep. 2010, pp. 1–4.
◾ H.-B. Le, J.-W. Nam, S.-T. Ryu, and S.-G. Lee, “A CMOS sigma-delta modulator for a digital electret microphone with a high input-impedance preamplifier,” 15th Korean Conference on Semiconductors, Phyeong-Chang, Feb. 2008.
◾ 김진석, 엄기윤, 강선구, 김창완, 남재원, A 60-GHz, 10-Gb/s PAM-4 CMOS 수신기, 2021년도 한국전자파학회 하계종합학술대회, 라마다프라다제주호텔, 2021남재원
◾ Soowang Park;Jae-Won Nam;Sandeep K. Gupta, SAT 하드웨어 가속기의 단일칩 구현을 위한 벤치마크, Proceeding of Asia and South Pacific Design Automation Conference, 교토, 2021남재원
◾ Kwon Hee won, Jaewon Nam, Joongheon Kim, Youn Kyu Lee, 지문에 대한 적대적 공격 인식 시스템, 제 35차 정보 및 네트워크 국제학술대회, 제주도 라마다호텔 비대면 발표, 2021남재원
◾ Jae-Won Nam, Youn Kyu Lee, 머신러닝 기반 아날로그 혼성신호 집적회로 설계 및 최적화기법, Proceeding of the 35th international Conference on Information Networking (ICOIN-2021), 대한민국 제주도 라마다 프라자호텔 (비대면 동시개최), 2021남재원
◾ Jae-Won Nam, 아날로그-디지털 신호변환기 기반 유선수신기, 제 3회 반도체공학회 종합학술대회, 양재 aT센터 (비대면 발표진행), 2020남재원
◾ Jae-Won Nam, Young-Deuk Jeon, Young-Kyun Cho, Sang-Gug Lee, and Jong-Kee Kwon, A 2.85mW 0.12mm^2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS, 2009 ESSCIRC 초록, 그리스 아테네, 2009남재원
특허
◾ J.-W. Nam, Y.-D. Jeon, Y.-K. Cho, J.-K. Kwon, “Algorithmic analog-to-digital converter,” US 7847713 B2.
◾ J.-W. Nam, Y.-D. Jeon, Y.-K. Cho, J.-K. Kwon, “Pipeline analog-to-digital converter,” US 8164497 B2.
◾ S.-C. Lee, J.-W. Nam, Y.-D. Jeon, J.-K. Kwon, “Method of algorithmic analog-to-digital conversion and algorithmic analog-to-digital converter,” US 7705764 B2.
◾ M. H. Cho, Y. G. Kim, J.-W. Nam, and J.-K. Kwon, “Read-out circuit with high input impedance,” US 8300850 B2.
◾ Y.-D. Jeon, Y.-K. Cho, J.-W. Nam, J.-K. Kwon, “Multi-stage successive approximation register analog-to-digital converter and analog-to-digital converting method using the same,” US 7999719 B2.
◾ Y.-D. Jeon, Y.-K. Cho, J.-W. Nam, J.-K. Kwon, “Multi-stage dual successive approximation register analog-to-digital convertor and method of performing analog-to-digital conversion using the same,” US 7978117 B2.
◾ Y.-K. Cho, Y.-D. Jeon, J.-W. Nam, J.-K. Kwon, “High-speed multi-stage voltage comparator,” US 7977979 B2.
◾ Y.-D. Jeon, Y.-K. Cho, J.-W. Nam, J.-K. Kwon, “Reference voltage supply circuit including a glitch remover,” US 8547081 B2.
◾ Y.-K. Cho, Y.-D. Jeon, J.-W. Nam, J.-K. Kwon, “Successive approximation register analog-digital converter and method for operating the same,” US 8164504 B2.
◾ Y.-K. Cho, Y.-D. Jeon, J.-W. Nam, J.-K. Kwon, “Successive approximation register analog-digital converter and method of driving the same,” US 7893860 B2.
◾ Y.-K. Cho, Y.-D. Jeon, J.-W. Nam, J.-K. Kwon, “Digital-to-analog converter,” US 8059022 B2.
◾ Y.-K. Cho, Y.-D. Jeon, J.-W. Nam, J.-K. Kwon, “Offset-voltage calibration circuit,” US 8264268 B2.

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